Omnivision examiner use only 2005 china career fair exam 1 logic design e is a fifo design which the clock of data input is running at100mhz,while the clock of data output is running at inputdata is a fix pattern .800 input clocks carry in 800 datacontinuously,and the other 200 clocks carry in no big the fifoshould be in order to avoid data over/under_run?please select theminimum depth below to meet the requirement. A.160 b.200 c.800 d .1000 osedly there is acombinational circuit between two registersdriven by a will you do if the delay of the combinationalcircuit is greater than the clock signal? reduce clock frequency increase clock frequency make it pipelining d to make it multi_cycle h of the follow circuits can generate gitch free gated_clk? ys@(posedge clk) gated <=en;assign gated_clk=gated&~clk; ys@(negedge clk) gated <=en;assign gated_clk=gated&~clk; ys@(posedge clk) gated <=en;assign gated_clk=gated|~clk; ys@(negedge clk) gated <=en;assign gated_clk=gated|~clk; ’re working on a specification of a system with some parameter has min,typ and max h columnwould you put setup and hold time? p time in max,hold time in min p time in min,hold time in max in max in min e are 3 ants at 3corners of a triangle. They randomly startmoving towards another is the probability that won’tcollide? a.0 b.1/8 c/1/4 d.1/3 you look at a clock and the time is 3: is angle between the hour and the minute hand? a.0 b.360/48 3.360/12 d.360/4 many times per day a clock’s hands overlap? a.11 b.22 c.24 d.26 8.d flip-flop :t_setup=3 ns; t_hold =1 ns; t_ck2q= is the max clock frequency the circuit can handle? A.200mhz b.250mhz c.500mhz d.1ghz ical design re tape-out,which routine check should be performed for your layout database in 0.18 um process?
&antenna lation to fix antenna effect? the wire wider and shorter ge lower metal to upper metal ect with diode of metal and diffusion ge upper metal to lower metal e.b&c se expain lvs c versus schematic ut versus schematic ut via synthesis c via synthesis to control clock skew? balanced clock tree ease the fanout clock buffer evenly ease clock latency to avoid hold_time violation? r the clock speed clock arrive later clock arrive earlier data arrive later data arrive earlier kinds of factors reflect good floor plan? routing timing met gh power supply d.a&b e.a&b&c cause cell delay? t-pin transition time ut-pin capacitance. ut-pin resistance d.a&b e.b&c need i/o pads for each chip? protection age level shift h-up prevention d.a&c e.a&b&c h one is worse-case in 0.18um process? 1.1.8v,25c 2.1.98v,125c 3.1.62v,-40c 4.1.62v,125c 5.1.98v,-40c power plan is not good,what’ll happen to the chip? a.hot-spot age drop ng not met ing is tough of above itecture design are two images,the first image has a person in front of ablackboard in a classroom and the second image has a person in front ofa lush two images are compressed using the jpeg algorithm. first image will have larger file size. second image will have a larger file size. would you round a 10b number,x,at the 3rd(上角)bit? a.(x>>2)<<2. b.(x>>3)<<3. c.((x+4)>>2)<<2 d.((x+4)>>2)<<3 e.((x+8)>>2)<<3 f.((x+8)>>3)<<3 happens if the number in 2 is negative? A ignore it absolute ,do the operation in 2,and add sign back of the above would you multiply a 4 in hardware? 4 adders each is offset from the provious adder by 1bit. a booth multip;ier with 4b coefficient. wires. a barrel shifter. is a fifo?what is a filo?which one is a queue? Which one is a stack? is a queue and filo is a stack. is the name of a dog. Filo is the name of a cat. is a stack and filo is a queue. would you design a barrel shifter? multiple stages of 2乘2 multiplexers a crossbar switch that can switch any inputs to any outputs a clos network muxes to switch between all combinations of hardwired shifts. 還有chip verification、algorithm design、hardware design、analog design。